The present invention relates to sequence processing technology in relation to a protocol used when a command or data is transmitted between a computer and a peripheral device via a transmission line.
The IEEE 1394 system has received attention as a next-generation interface for connection between audio-visual (AV) appliances, computers, and the like because the IEEE 1394 system defines both asynchronous communications and isochronous communications. Asynchronous communications is adopted for communication requiring reliability more than real-time capability, such as data transmission between a computer and a recording medium. Isochronous communications is adopted for communication requiring real-time capability rather than reliability, such as transmission of AV data including moving images. Therefore, for storing computer data in a DVD-RAM (digital versatile disc—random access memory) drive or reading computer data stored in a DVD-RAM drive, for example, according to IEEE 1394, data transmission is generally performed by asynchronous communications.
Serial bus protocol-2 (SBP-2) is a protocol for IEEE 1394 asynchronous communications between a device such as a computer (an initiator) and a peripheral device (a target). Hereinafter, a command processing sequence followed when a computer reads data from a target such as a DVD-RAM drive according to SBP-2 will be described.
SBP-2 commands may be grouped into command-type commands such as READ and WRITE and management-type (task management-type) commands such as LOGIN, QUERY LOGIN, ABORT TASK, and ABORT TASK SET.
FIG. 9 is a diagram illustrating a command processing sequence for executing LOGIN command as a management-type command. Referring to FIG. 9, a command processing sequence for LOGIN command will be described.
(1) An initiator issues a quadlet read request (QRRQ) packet to acquire unique information (such as device information) of a target. In general, the unique information is entirely stored in an area called a configuration ROM (configROM), and contains the address of a MANAGEMENT_AGENT register of the target.
(2) In response to the QRRQ packet from the initiator, the target returns configROM data to the initiator as a quadlet read response (QRRS) packet. The process steps (1) and (2) of transmitting the QRRQ and QRRS packets continue until the initiator acquires all of configROM data.
(3) The initiator issues a block write request (BWRQ) packet, writing the address of a memory storing an operation request block (ORB) in the MANAGEMENT_AGENT register. The ORB is prepared in advance by the initiator. The MANAGEMENT_AGENT register exists in a control and status register (CSR) space of the target.
(4) In response to the BWRQ packet from the initiator, the target returns a write response (WRS) packet to the initiator.
(5) The target issues a block read request (BRRQ) packet to the initiator, requesting transmission of the ORB to the target. The ORB is located at a position specified by the address stored in the MANAGEMENT_AGENT register.
(6) In response to the BRRQ packet from the target, the initiator returns a block read response (BRRS) packet to the target. The ORB is stored in a data field of the BRRS packet. In this way, the ORB is transmitted from the initiator to the target.
(7) The target receives the ORB from the initiator and analyzes the content of the received ORB.
(8) Once finding out that the received ORB represents LOGIN command, the target executes the LOGIN command. LOGIN response during the execution of the command contains the base address of a COMMAND_AGENT register.
(9) Once the execution of the LOGIN command is terminated, the target prepares status information indicating the execution results of the LOGIN command.
(10) The target issues a BWRQ packet, transmitting the status information to the initiator. The status information is stored in a predetermined address designated by the ORB (Status_FIFO address in the initiator).
(11) In response to the BWRQ packet from the target, the initiator returns a WRS packet to the target.
(12) The target determines whether or not rCode in the WRS packet from the initiator is resp_complete. If the rCode in the WRS packet from the initiator is resp_complete, the command processing sequence for the LOGIN command is completed.
FIG. 10 is a diagram illustrating a command processing sequence for executing READ command as a command-type command. The sequence of FIG. 10 is executed after the termination of the LOGIN command processing sequence described with reference to FIG. 9. Referring to FIG. 10, the command processing sequence for READ command will be described.
(21) The initiator prepares an ORB representing READ command, which defines information required for execution of the READ command, such as the data amount, the maximum packet length, the transfer direction, and the transfer method.
(22) The initiator writes a QWRQ packet in an AGENT_RESET register of the target to initialize the target. The AGENT_RESET register exists in the CSR space of the target.
(23) In response to the QWRQ packet from the initiator, the target returns a WRS packet to the initiator.
(24) The initiator issues a BWRQ packet, writing the address in a memory storing the ORB in an ORB_POINTER register. The ORB_POINTER register exists in the CSR space of the target.
(25) In response to the BWRQ packet from the initiator, the target returns a WRS to the initiator.
(26) The target issues a BRRQ packet to the initiator, requesting transmission of the ORB to the target. The ORB is located at a position specified by the address stored in the ORB_POINTER register, that is, at the address in the memory of the initiator.
(27) In response to the BRRQ packet from the target, the initiator returns a BRRS packet to the target. The ORB is stored in a data field of the BRRS packet. In this way, the ORB is transmitted from the initiator to the target.
(28) The target receives the ORB from the initiator and analyzes the content of the received ORB.
(29) Once finding out that the received ORB represents READ command, the target executes the READ command. During the execution of the READ command, the following process steps (30) and (31) are repeated. This is because when the size of data to be transferred is large, the data must be transferred in the form of a plurality of packets. The data to be transferred is prepared by the target.
(30) The target issues a BWRQ packet, transmitting the data to an address designated by the ORB.
(31) In response to the BWRQ packet from the target, the initiator returns a WRS packet to the target. The process steps (30) and (31) constitute one transaction. After it is confirmed that one transaction has been normally terminated, the next transaction is executed.
(32) Once the data transfer sequence is normally terminated, the target prepares status information indicating the execution results of the READ command.
(33) The target issues a BWRQ packet, transmitting the status information to the initiator. The status information is stored in a predetermined address designated by the ORB.
(34) In response to the BWRQ packet from the target, the initiator returns a WRS packet to the target.
(35) The target determines whether or not rCode in the WRS packet from the initiator is resp_complete. If the rCode in the WRS packet from the initiator is resp_complete, the command processing sequence for the READ command is completed.
Note that although not illustrated in FIGS. 9 and 10, the target returns an acknowledge (ACK) packet to the initiator whenever it receives a packet from the initiator, and the initiator returns an ACK packet to the target whenever it receives a packet from the target.
When receipt of a write request packet (for example, BWRQ, QWRQ) is successful, the initiator or the target returns an ACK packet having a code of “Ack_complete” indicating success of receipt of the packet. In this case, no WRS packet is returned and the process proceeds to the next step. When the initiator or the target returns an ACK packet having a code of “Ack-pending”, it returns a WRS packet. When the initiator and the target are in a state of being unable to receive a packet for any reason, they return an ACK packet having a code of “Ack_busy” indicating the state of being unable to receive a packet. In the data transfer sequence, when the initiator returns an ACK packet having a code of “Ack_busy” to the target in response to a BWRQ packet from the target, the target re-transmits the BWRQ packet to the initiator.
In the manner described above, the data transfer processing can be performed between the initiator and the target. In SBP-2, up to 63 initiators at maximum can be connected to one target on one bus.
FIG. 11 is a block diagram of a conventional sequence processor 90 that implements SBP-2. A physical layer controller 91 has functions such as initialization, arbitration, and bias voltage control of an IEEE 1394 bus 20. An link core circuit 92 receives a packet on the bus 20 via the physical layer controller 91, and performs preparation/detection of an error detection code, addition of the error detection code to a packet, detection of a code (for example, a code in an ACK packet), and the like. The link core circuit 92 also outputs a packet to the bus 20 via the physical layer controller 91. In addition, the link core circuit 92 has a retry function of retrying transfer of a packet of which transfer has once failed.
A packet filter 93 receives the packet output by the link core circuit 92, and analyzes the content of a header field of the packet. The packet filter 93 sends a control signal to a sequence control circuit 99 or a transfer control circuit 96 depending on the analysis results, as well as outputting the received packet to a packet processing circuit 95. The packet processing circuit 95 processes the input packet and outputs a command to a command receive buffer 97 or outputs the received data externally via a direct memory access (DMA) bus 6, under control of the sequence control circuit 99 or the transfer control circuit 96. The sequence control circuit 99 performs execution and control of a command processing sequence for one connected initiator.
As described above, the conventional sequence processor of FIG. 11 performs a command processing sequence involving one initiator.
For the conventional sequence processor to perform a command processing sequence for two or more initiators, it is necessary to perform all of the sequence processing for the second and subsequent initiators and the management of the respective initiators by firmware. This greatly increases the load on a central processing unit (CPU).
In particular, when a large amount of data handled by an optical disc device such as a DVD-RAM is transferred, the load on a CPU dramatically increases. This increases the overhead of firmware executed by the CPU, and as a result, makes it quite difficult to attain a high effective transfer rate required for a high-speed serial bus interface, which should actually be attained by adopting IEEE 1394. In addition, since the load on the CPU is great when all of the above processing is performed by firmware, the sequence processor cannot be incorporated in another system such as an optical disc device.
As described above, the conventional sequence processor is actually applicable only to an occasion including a single initiator. Therefore, the conventional sequence processor is low in extensibility and is not so effectively usable in a network environment including a plurality of initiators.